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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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STM32F769IDiscovery
1.00
uDANTE Audio Networking with STM32F7 DISCO board
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Macros | |
| #define | ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) |
| Bit definition of RDES0 register: DMA Rx descriptor status register. More... | |
| #define | ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) |
| #define | ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) |
| #define | ETH_DMARXDESC_ES ((uint32_t)0x00008000U) |
| #define | ETH_DMARXDESC_DE ((uint32_t)0x00004000U) |
| #define | ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) |
| #define | ETH_DMARXDESC_LE ((uint32_t)0x00001000U) |
| #define | ETH_DMARXDESC_OE ((uint32_t)0x00000800U) |
| #define | ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) |
| #define | ETH_DMARXDESC_FS ((uint32_t)0x00000200U) |
| #define | ETH_DMARXDESC_LS ((uint32_t)0x00000100U) |
| #define | ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) |
| #define | ETH_DMARXDESC_LC ((uint32_t)0x00000040U) |
| #define | ETH_DMARXDESC_FT ((uint32_t)0x00000020U) |
| #define | ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) |
| #define | ETH_DMARXDESC_RE ((uint32_t)0x00000008U) |
| #define | ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) |
| #define | ETH_DMARXDESC_CE ((uint32_t)0x00000002U) |
| #define | ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) |
| #define | ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) |
| Bit definition of RDES1 register. More... | |
| #define | ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) |
| #define | ETH_DMARXDESC_RER ((uint32_t)0x00008000U) |
| #define | ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) |
| #define | ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) |
| #define | ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of RDES2 register. More... | |
| #define | ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) |
| Bit definition of RDES3 register. More... | |
| #define | ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ |
| #define | ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ |
| #define | ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ |
| #define | ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ |
| #define | ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ |
| #define | ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ |
| #define | ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ |
| #define | ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ |
| #define | ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ |
| #define | ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ |
| #define | ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ |
| #define | ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ |
| #define | ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ |
| #define | ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ |
| #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ |
Definition at line 892 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ |
Definition at line 894 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ |
Definition at line 893 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ |
Definition at line 895 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ |
Definition at line 898 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ |
Definition at line 897 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ |
Definition at line 896 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ |
Definition at line 891 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ |
Definition at line 890 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ |
Definition at line 881 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ |
Definition at line 882 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ |
Definition at line 885 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ |
Definition at line 886 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ |
Definition at line 884 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ |
Definition at line 887 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ |
Definition at line 888 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ |
Definition at line 889 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ |
Definition at line 883 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ |
Definition at line 880 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ |
Definition at line 904 of file stm32f7xx_hal_eth.h.
| #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ |
Definition at line 901 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) |
DA Filter Fail for the rx frame
Definition at line 831 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of RDES2 register.
Buffer1 Address Pointer
Definition at line 862 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) |
Bit definition of RDES3 register.
Buffer2 Address Pointer
Definition at line 867 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) |
CRC error
Definition at line 847 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) |
Dribble bit error: frame contains non int multiple of 8 bits
Definition at line 846 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) |
Descriptor error: no more descriptors for receive frame
Definition at line 834 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) |
Bit definition of RDES1 register.
Disable Interrupt on Completion
Definition at line 853 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) |
Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
Definition at line 833 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) |
Receive descriptor frame length
Definition at line 832 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) |
First descriptor of the frame
Definition at line 839 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) |
Frame type - Ethernet, otherwise 802.3
Definition at line 843 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) |
IPC Checksum Error: Rx Ipv4 header checksum error
Definition at line 841 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) |
Late collision occurred during reception
Definition at line 842 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) |
Frame size not matching with length field
Definition at line 836 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) |
Last descriptor of the frame
Definition at line 840 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) |
Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
Definition at line 848 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) |
Overflow Error: Frame was damaged due to buffer overflow
Definition at line 837 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) |
Bit definition of RDES0 register: DMA Rx descriptor status register.
OWN bit: descriptor is owned by DMA engine
Definition at line 830 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) |
Receive Buffer1 Size
Definition at line 857 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) |
Receive Buffer2 Size
Definition at line 854 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) |
Second Address Chained
Definition at line 856 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) |
Receive error: error reported by MII interface
Definition at line 845 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) |
Receive End of Ring
Definition at line 855 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) |
Receive Watchdog Timeout: watchdog timer expired during reception
Definition at line 844 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) |
SA Filter Fail for the received frame
Definition at line 835 of file stm32f7xx_hal_eth.h.
| #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) |
VLAN Tag: received frame is a VLAN frame
Definition at line 838 of file stm32f7xx_hal_eth.h.
1.8.11
