APB1 Peripheral Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Macros
#define	__HAL_RCC_WWDG_CLK_ENABLE()
#define	__HAL_RCC_PWR_CLK_ENABLE()
#define	__HAL_RCC_WWDG_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define	__HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

#define __HAL_RCC_PWR_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 472 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 463 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 471 of file stm32f7xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE

(

)

Value:

do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0)

Definition at line 455 of file stm32f7xx_hal_rcc.h.